Semiconductor memories are used to store information, often in conjunction with microprocessors or other control circuits. Typical memory devices are comprised of an array of memory cells together with various "peripheral" circuitry. Each memory cell is capable of storing usually just one piece of data typically in binary format, a logic "1" or "0." The memory cells are arranged in a grid or array of rows and columns. The array may have multiple components, i.e, subarrays, each of which has rows and columns. In either case, each row of memory cells corresponds to and is accessible by a word line, and each column of memory cells corresponds to and is accessible by bit lines, often a pair of bit lines. At or near each intersection of each row and pair of bit lines in the array is a respective memory cell. In order to write or read from a specific memory cell, the memory device must be told which cell(s) to access. This is done by reading an address and decoding it into a row address and a column address. Data stored in the memory cell may then be transferred to the dam lines for outputting by the semiconductor memory, or dam may be written into that addressed cell via the bit lines. Traditional memories often require that for each memory cell that is externally accessed, an address must initially be loaded. Hence, a string of multiple memory accesses could require multiple address loads equal to the number of accesses.
While this method of addressing is adequate for random memory access of individual memory cells, often memory accesses occur in streams or blocks of binary sequential memory cells. In response, synchronous or burst mode semiconductor memories have been developed. After a memory read or write, these memory devices will automatically increment sequentially the address of the memory cell being accessed. Such incrementing is done by implementing addresses in a sequence, using a counter to supply increments. The counter counts in a traditional sequence, i.e., 1,2,3,4,5, etc. (except the count is in binary rather than decimal form). "Binary sequential mode" refers to counting in a traditional sequence with the numbers represented in a binary format. An address circuit which automatically increments the address after each memory access allows a whole block of sequential data to be accessed without having to load a new address for each memory cell read or written. This significantly improves memory access speeds for blocks of sequential memory cells, because the number of address loads is greatly reduced. The automatic address incrementing is typically achieved by the use of a counter. This counter is distinguishable from counters in DRAM memory devices which increment for the purpose of automatic refresh.
Dynamic Random Access Memories (DRAMs) due to their nature are made up of memory cells that generally use charge stored in capacitors as the physical storage mechanism. The charge stored in such capacitors leaks away. This requires the memory cells to be refreshed, which generally is done at a periodic rate. This rate needs to be fast enough that each memory cell will be refreshed before the charge, representing data, stored in each memory cell capacitor leaks away. Entire rows of memory cells can be refreshed at the same time. By activating a row during a memory refresh cycle, all of the memory cells along the row will refresh the charge stored therein.
Early implementations of DRAMs required external refresh control. Many newer designs now incorporate this function into the memory device itself.
However, the counters for performing the automatic refresh function cycle through the memory array sequentially row by row, as opposed to memory cell by memory cell. Automatic refresh counters typically count in a binary sequential fashion only. Automatic refresh counters that are used for self-refresh purposes do not have to operate at high speeds since these counters are incremented at slow refresh rates.
Another common sequential memory access, made popular by some implementations of cache memories, is called an "interleave sequence" (sometimes referred to in the computer industry as an "Intel sequence"), where memory access is optimized by the use of an interleave pattern.
Cache memories are used to store copies of main memory data and are constituted by blocks of data called "pages." Caches circuits are often comprised of faster and consequently more expensive memory devices. Commonly accessed blocks of data are replicated in the cache to allow faster memory access in the areas of memory where access is most frequently occurring. The area in which memory accesses occur most frequently is not static, but changes. As it changes, the cache circuit will update itself by loading new blocks of memory or pages so it will always try to contain the areas where memory access is most common. Because of this, large blocks of data are frequently transferred between the cache memory and the main memory. Due to the nature of caches being arranged in blocks of data called pages, an Intel or interleave sequence has been developed to improve the efficiency of loading the processor's on-chip first level cache. Additionally, it allows a processor to load a cache beginning with an initial memory address in the middle of a page not currently loaded in the cache. The interleave sequence will guarantee that the rest of the page will be loaded into the cache in its entirety. Therefore, it is beneficial when memory address circuits contained counter circuits capable of counting in interleave sequential mode, for such events as cache loading (when the processor is involved) and in binary mode, for such events as reading a disk (when the processor is usually not involved).
In order to help illustrate how a counter circuit is incorporated into a memory device for generating sequential addresses, reference is made to a prior art circuit 140 of FIG. 1. Circuit 140 includes a memory cell array 142 which receives inputs from row decoders 144, column decoders 146 and input buffers 148. Array 142, cooperating with sense amplifiers (not separately shown) generates outputs to output buffers 150. Input buffers 148 and output buffers are used for data which is to be retrieved from or stored in the array. Decoders 144 and are used to select a unique row and column. Each combination of row and column will address a unique memory cell within the array. Address decoders 144 and 146 receive address lines from the address latch 152. The address latch can be directly loaded from the input buffers or from a counter 144. Counter circuit 154 receives a starting count value from input buffers 148. As a result, a counter circuit such as counter 154 can be used to generate addresses for a memory circuit. Current synchronous or burst mode DRAMs are similarly configured.
TABLE 1 ______________________________________ BINARY/INTERLEAVE ADDRESSING SEQUENCE Sequential Interleave START ADDRESS Addressing Addressing ______________________________________ BURST LENGTH OF TWO 0 0,1 0,1 1 1,0 1,0 BURST LENGTH OF FOUR 00 0,1,2,3 0,1,2,3 01 1,2,3,0 1,0,3,2 10 2,3,0,1 2,3,0,1 11 3,0,1,2 3,2,1,0 BURST LENGTH OF EIGHT 000 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 001 1,2,3,4,5,6,7,0 1,0,3,2,5,4,7,6 010 2,3,4,5,6,7,0,1 2,3,0,1,6,7,4,5 011 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,4 100 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 101 5,6,7,0,1,2,3,4 5,4,7,6,1,0,3,2 110 6,7,0,1,2,3,4,5 6,7,4,5,2,3,0,1 111 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0 ______________________________________
Table 1 shown here provides a chart for 1 bit, 2 bit, and 3 bit sequential count sequences for both binary and interleave modes. While binary mode counting progresses in a traditional counting sequence, interleave mode counting may vary significantly, depending on the starting count value. In interleave mode, the first bit (least significant bit), will toggle every count increment. The second bit will toggle on every second count increment, i.e., on the second, fourth, sixth, eighth, etc., count increments. The third bit will toggle on every fourth count increment, i.e., or on the fourth, eighth, twelfth, etc., count increments. The (n)th bit will toggle on every (2.sup.N-1)th count increment.
With industry pushing for higher performance systems and as memory access becomes more of a bottleneck with ever increasing microprocessor speeds, increased memory access speeds are becoming more important.
It is therefore an object of the present invention to provide a counter circuit to be used in conjunction with address lines to automatically increment the address in both a binary and an interleave sequence in order to increase access speeds for blocks of sequential dam in semiconductor memories.
Another object of the invention is to allow real time switching between the two modes of sequential block memory access. This will allow for even greater addressing flexibility.